SV7C Personalized SerDes Tester

The SV7C Personalized SerDes Tester from Introspect Technology is a cutting-edge, parallel high-speed test solution tailored for today’s complex electronic components and board designs. Supporting data rates up to 28 Gbps, the SV7C features 16 independent pattern generators and 16 independent signal/data analyzers, offering comprehensive and phase-aligned bit error rate testing (BERT), as well as protocol exercising and analysis for interfaces like PCIe, Ethernet, USB, and JESD204C.

This all-in-one platform enables per-lane jitter tolerance testing with independent jitter injection, voltage and skew control, and hardware clock recovery (CDR). It also provides source-synchronous bus testing with auto-calibrated phase delays and intuitive scripting via a Python-based environment. With support for single-ended and differential low-speed I/O, the SV7C offers robust out-of-band device control.

By integrating tools such as a pattern generator with feed-forward equalization, an error detector with programmable EQ and CDR, a protocol exerciser, and protocol analyzer, the SV7C delivers unmatched visibility into signal integrity, crosstalk, and channel behavior in highly parallel SerDes systems.

  • Parallel (x16) jitter tolerance testing with per-lane jitter injection control
  • Per-lane voltage, skew, and noise injection control
  • Per-lane transmit and receiver equalization and per-lane hardware clock recovery (CDR)
  • Source-synchronous bus testing with auto-calibrated phase delays
  • State of the art programming environment based on the highly intuitive Python language
  • Single-ended or differential low-speed digital I/O for out of band device control

The SV7C is a parallel high-speed tester that meets the emerging test and validation requirements of increasingly complex electronic component and board designs. Operating at up to 28 Gbps and featuring 16 independent pattern generators and 16 independent signal/data analyzers, the SV7C is an all-in-one, phase-aligned bit error rate tester (BERT) and protocol exerciser and analyzer, providing self-contained functional and physical layer test and measurement capabilities for interfaces such as PCIe, Ethernet, USB, and JESD204C.

The SV7C integrates multiple tools into one – a pattern generator with feed-forward equalization, an error detector with programmable equalization and clock recovery, a full-functional protocol exerciser, and a full-functional protocol analyzer. It provides unprecedented insights into crosstalk and channel-to-channel variations in highly parallel systems.

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